History
Work¶
- 2009-2019: IBM's T.J. Watson Research Lab — Research Staff Member
- 2008-2009: University of Michigan — Postdoctoral Researcher
- 1998-2002: Analog Devices Inc., Ireland — Design Engineer
Education¶
- 2003-2008: Ph.D., University of Michigan
- 1994-1998: B.E., National University of Ireland, Cork (UCC)
Topics¶
- Self-healing PLLs
- Fractional-N noise cancellation
- Varactor folding
- Flicker noise suppression in VCOs
- Software for phase arrays
Self-healing PLLs
Ferriss, M.; Plouchart, J.-O.; Natarajan, A.; Rylyakov, A.; Parker, B.;
Babakhani, A.; Yaldiz, S.; Sadhu, B.; Valdes-Garcia, Alberto; Tierno, J.; Friedman, D.,
"An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS,"
VLSI Circuits (VLSIC), 2012.
Single and dual path PLLs¶
- Split control path into proportional and integral path e.g: [Craninckx, JSSC 1998]
Requires two charge-pumps and two VCO varactors
Why use this architecture?
Effects of non-linearity and offsets¶
- Saturation corrupts measurement when step is large
- Offset corrupts measurement when step is small
Time-to-crossover in presence of offsets¶
Real measurement has offsets caused by: Charge pump current mismatch, capacitor leakage, BB-PFD offset, etc.
PLL response to a phase step, with no proportional path¶
- Saturation corrupts measurement when step is large
- Offset corrupts measurement when step is small
Wafer level test¶
Measured jitter peaking (in dB) before/after calibration. Tested every die on a 300mm wafer at 25GHz
Improved uniformity shown across wafer
Parametric phase noise healing¶
Noise @10MHz = f( VCO fnom, Amplitude, Bias Voltage and Current, VCC, Band )
Methodology described in: S. Yaldiz, V. Calayir, X. Li, L. Pileggi, A. Natarajan, M. Ferriss and J. Tierno, “Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators,” IEEE CICC, Mar. 2011.
Fractional-N noise cancellation
Ferriss, M.; Sadhu, B.; Rylyakov, A.; Ainspan, H.; Friedman, D.,
"A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme,"
IEEE International Solid- State Circuits Conference (ISSCC), 2015.
Classic $\Delta\Sigma$ Problem¶
- Divider’s $\Delta\Sigma$ dithers PLL’s feedback (FB) clock
- $\Delta\Sigma$ noise contributes to PLL’s phase noise
Time-based Cancellation Concept¶
- Digital-to-time based delay scheme used on analog path
- Utilizes loop filter’s low pass response to remove delay path quantization noise -> Don’t need fine quantization step.
Delay Controller Architecture¶
Controller’s function is to:
(1) Background calibrate DTC gain, (2) Shape $\Delta$T quantization error, and (3) Shape the mismatch error
Integral Path Prediction Circuit¶
- Integral path operates from single BB phase detector
- Works in parallel with the analog proportional path
- Ignores BB results that match prediction
Transient Locking¶
Response to step in division ratio measured with sampling scope.
Measured with different integral path gain settings (green, red), and with direct loading of digital control word (blue).
Varactor Folding
Ferriss, M.; Sadhu, B.; Rylyakov, A.; Ainspan, H.; Friedman, D.,
“A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs,"
IEEE International Solid-State Circuits Conference (ISSCC), 2016.
Motivation¶
- Objective: Remove coarse bands of CMOS oscillators
- Utilize entire tuning range to generate frequency chirps
Varactor gain versus frequency¶
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Flicker noise suppression in VCOs
Ferriss, M.; Sadhu, B.; Friedman, D.;
"A Gradient Descent Bias Optimizer for Oscillator Phase Noise Reduction Demonstrated in 45nm and 32nm SOI CMOS,"
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018.
Transconductance¶
Transconductor with odd I-V characteristic => no up-conversion from DC to phase noise. [Pepe, Andreani TCAS I, 2017]
45nm, bias scheme enabled, disabled, and swept
32nm with tail inductor, bias scheme enabled, disabled
Software for phased arrays
Sadhu, B.; Paidimarri, A.; Ferriss, M.; Yeck, M.; Gu, X.; Valdes-Garcia, A.,
"A Software-Defined Phased Array Radio with mmWave to Software Vertical Stack Integration for 5G Experimentation,"
2018 IEEE/MTT-S International Microwave Symposium - (IMS), 2018.
Sadhu, B.; Tousi, Y.; Hallin, J.; Sahl, S.; Reynolds, S.; Renström, Ö.; Sjögren, K.; Haapalahti, O.; Mazor, N.; Bokinge, B.; Weibull, G.; Bengtsson H.; Carlinger, A.; Westesson E., Thillberg, J.; Rexberg, L.; Yeck M. , Gu X.; Ferriss M.; Liu, D.; Friedman, D.; Valdes-Garcia, A.,
"A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications”
IEEE Journal of Solid-State Circuits, 2017. Awarded JSSC 2017 Best Paper.
Photograph of the SDPAR system.
Beam optimization (Software)¶
An optimization experiment using the SDPAR software emulator where the optimizer creates a beam pattern to improve signal to interference ratio starting from an arbitrary beam.
